1. Field of Invention
The present invention relates to a method of manufacturing metal interconnects. More particularly, the present invention relates to a dual damascene manufacturing process that uses a tungsten chemical-mechanical polishing (W-CMP) operation.
2. Description of Related Art
In the manufacturing process of very large scale integration (VLSI) circuits, semiconductor devices are linked by two or more metallic interconnects commonly known as multilevel interconnects. The purpose of having multilevel interconnects is to establish a three-dimensional wiring structure so that devices can be interconnects even when device density continues to increase. Normally, a first metallic wiring layer is formed over a substrate. The first layer can be a polysilicon or a metallic layer and the first layer is electrically connected to one of the source/drain regions of a device embedded in the substrate. For the interconnection of additional devices, a second or more layers can be subsequently formed on top of the first layer. However, as the level of integration continues to increase, capacitance effect of the metallic wires will also increase correspondingly. Consequently, RC delay and cross talk between vias will tend to intensify and the speed of transmission by the metallic wires will be slower.
At present, a new method of manufacturing metal interconnects known as a dual damascene process has been developed. Using the dual damascene process, high-quality metal interconnect structures can be manufactured. One major characteristic of the dual damascene process is the simultaneous etching of metallic wire pattern and via structures. The dual damascene process includes the steps of first depositing an insulating layer such as a silicon dioxide layer over a semiconductor substrate. Then, photolithographic and anisotropic etching operations are conducted to form a trench in the insulating layer. The trench is formed in location where the metallic wire pattern is desired. In addition, the trench is formed such that depth of the trench is not deep enough to penetrate the insulating layer. Next, another set of photolithographic and etching operations are conducted to form a via opening in the insulating layer such that a portion of the semiconductor substrate is exposed.
Generally, the width of a via opening is smaller than the width of the trench above. Thereafter, metal such as tungsten is deposited to fill the trench and the via opening. Subsequently, a chemical-mechanical polishing (CMP) operation is carried out to remove a portion of the metallic layer above the trench surface, thereby forming a metallic wire pattern electrically linked to other devices or another wire pattern below through a via.
FIG. 1 is a cross-sectional view showing a conventional dual damascene structure. In FIG. 1, an insulating layer 12 made from material such as silicon dioxide is formed above a semiconductor substrate 10. Within the insulating layer 12, a metallic wiring layer 16b is formed above a via 16a, both of which are made from tungsten. In addition, a glue layer is formed between the metal wiring layer 16b and the insulating layer 12 as well as between the via 16a and the insulating layer 12. The glue layer 14 is normally a titanium/titanium nitride (Ti/TiN) composite layer or a layer made from other refractory metals. The purpose of forming the glue layer 14 is to increase adhesion between the metallic wiring layer 16b and the insulating layer 12.
However, using the aforementioned dual damascene process often results in dishing on the surface of the metallic wiring layer. This is because the excess tungsten above the metallic wiring layer 16b is normally removed by a chemical-mechanical polishing method. A difference in polishing selectivity will generate a non-planar or a dish surface 19 as shown in FIG. 1. Using a Ti/TiN glue layer as an example, polishing selectivity between tungsten (W) and titanium (Ti) is roughly 3:1.about.5:1.
However, the polishing selectivity between tungsten (W) and titanium nitride (TiN) is about 1:1. Due to a difference in polishing rate between titanium and tungsten when the titanium layer is polished, a dish surface 19 will form on the surface of the metallic wiring layer 16b. The dish surface 19 can compromise the resulting quality of subsequently deposited layers. In serious cases, oxide erosion or the so-called volcano effect may occur. Moreover, a portion of the residual refractory metal will remain on top of the glue layer 14 after polishing. Therefore, unwanted bridges that may lead to short-circuiting can be produced.
Conventionally, the only remedy for rectifying the dishing effect is to perform multiple polishings with different slurries and polishing pads so that the problem of high polishing selectivity can be reduced. However, multiple polishing will lead to an increase in the amount of rework, thereby raising the production cost.
In light of the foregoing, there is a need to provide an improve method of forming a dual damascene structure.